Exemplary embodiments of the present invention relate to a clock control circuit for synchronization control of a semiconductor memory device, and a method for operating a semiconductor memory device including a clock control circuit.
For a high speed operation, a semiconductor memory device is designed to receive an external clock signal and process commands and data in synchronization with the external clock signal. The external clock signal inputted to the semiconductor memory device is one of the main factors contributing to power dissipation because it is always toggling under operation conditions of the semiconductor memory device.
FIGS. 1 and 2 are diagrams of a clock control circuit which is used in a known semiconductor memory device.
As shown, the known clock control circuit includes a first clock buffer 14 of FIG. 1 and a second clock buffer 28 of FIG. 2. When a first clock buffer enable signal CLKBUF1_EN is activated to a logic high level, the first clock buffer 14 converts clock signals CLK and CLKB to generate first internal clock signals ICLK2F and ICLK2. When a second clock buffer enable signal CLKBUF2_EN is activated to a logic high level, the second clock buffer 28 converts the clock signals CLK and CLKB to generate second internal clock signals CVR_CLK2 and CVR_CLK1B.
The first clock buffer enable signal CLKBUF1_EN for controlling the first clock buffer 14 transitions to a logic high level when a valid self-refresh operation signal SREF_FASTB is at a logic high level and an inverted external reset signal RSTB is at a logic high level. Here, the valid self-refresh operation signal SREF_FASTB is activated in response to an input timing of an external self-refresh start command signal SREF_CMD, and deactivated in response to an input timing of an external self-refresh exit command signal EXIT_CMD.
The first clock buffer 14 generates the first internal clock signals ICLK2F and ICLK2 by converting the clock signals CLK and CLKB in response to the high-level first clock buffer enable signal CLKBUF1_EN. Except for a self-refresh period, the first internal clock signals ICLK2F and ICLK2 are always toggling and are provided to control a specific internal block 10 and a self-refresh signal generation unit 20. Therefore, when the semiconductor memory device is operating, the first clock buffer 14 always consumes an electric current during the toggling operation. For reference, the specific internal block 10 may include an On Die Termination (ODT) block and a delay locked loop (DLL) circuit, which are activated in advance prior to a main operation of the semiconductor memory device.
The clock buffer enable signal CLKBUF2_EN for controlling the second clock buffer 28 transitions to a logic high level when both an internal self-refresh signal SREF and a power-down signal PWR_DN are at a logic low level and the inverted external reset signal RSTB is at a logic high level. Here, the internal self-refresh signal SREF is activated to a logic high level for a period where a substantial self-refresh operation is performed, and the power-down signal PWR_DN is activated to a logic high level for a power-down mode of the semiconductor memory device.
The second clock buffer 28 generates the second internal clock signals CVR_CLK2 and CVR_CLK1B by converting the clock signals CLK and CLKB in response to the high-level second clock buffer enable signal CLKBUF2_EN. Except for the self-refresh period, the second internal clock signals CVR_CLK2 and CVR_CLK1B are always toggling and are provided to control a plurality of internal blocks 30 to 36. Therefore, when the semiconductor memory device is operating, the second clock buffer 28 also always consumes an electric current during the toggling operation. For reference, the internal blocks 30 to 36 may include a command decoding unit which is activated for the main operation of the semiconductor memory device.
Hereinafter, referring to FIGS. 1 and 2, an operation of the clock control circuit of a known semiconductor memory device is described below.
FIG. 3 is a timing diagram depicting a case where an internal operation of the semiconductor memory device is in an idle state after a self-refresh control operation is completed.
Referring to FIG. 3, when the self-refresh start command signal SREF_CMD is input, a clock enable signal CKE and the idle signal IDLE are deactivated to a logic low level, the valid self-refresh operation signal SREF_FASTB is activated to a logic low level, and the internal self-refresh signal SREF is activated to a logic high level. In response to the low-level valid self-refresh operation signal SREF_FASTB, the first clock buffer enable signal CLKBUF1_EN is deactivated to a logic low level, and thus the first clock buffer 14 stops a toggling of the first internal clock signal ICLK2. Meanwhile, in response to the high-level internal self-refresh signal SREF, the second clock buffer enable signal CLKBUF2_EN is deactivated to a logic low level, and thus the second clock buffer 28 stops a toggling of the second internal clock signal CVR_CLK2.
After an internal self-refresh operation is performed, the self-refresh exit command signal EXIT_CMD is input. In response to the self-refresh exit command signal EXIT_CMD, the clock enable signal CKE is activated to a logic high level and the valid self-refresh operation signal SREF_FASTB is deactivated to a logic high level. At this time, the idle signal IDLE becomes a logic high level since there are no low-active banks among internal banks of the semiconductor memory device. In response to the high-level valid self-refresh operation signal SREF_FASTB, the first clock buffer enable signal CLKBUF1_EN is activated to a logic high level, and thus the first clock buffer 14 starts toggling of the first internal clock signal ICLK2. The self-refresh signal generation unit 20 deactivates the internal self-refresh signal SREF to a logic low level in response to the toggling of the first internal clock signal ICLK2, and thus, the second clock buffer enable signal CLKBUF2_EN is activated to a logic high level. Accordingly, the second clock buffer 28 starts toggling of the second internal clock signal CVR_CLK2.
FIG. 4 is a timing diagram depicting a case where the internal operation of the semiconductor memory device is not in an idle state after a self-refresh control operation is completed.
Referring to FIG. 4, when the self-refresh start command signal SREF_CMD is input, the first clock buffer 14 stops a toggling of the first internal clock signal ICLK2 and the second clock buffer 28 stops a toggling of the second internal clock signal CVR_CLK2, as described in FIG. 3.
After the internal self-refresh operation is performed, the self-refresh exit command signal EXIT_CMD is input. In response to the self-refresh exit command signal EXIT_CMD, the clock enable signal CKE is activated to a logic high level and the valid self-refresh operation signal SREF_FASTB is deactivated to a logic high level. At this time, the idle signal IDLE maintains a logic low level since at least one bank is activated. In response to the high-level valid self-refresh operation signal SREF_FASTB, the first clock buffer enable signal CLKBUF1_EN is activated to a logic high level, and thus the first clock buffer 14 starts toggling of the first internal clock signal ICLK2. However, the self-refresh signal generation unit 20 maintains the internal self-refresh signal SREF at a logic high level until the idle signal IDLE is activated to a logic high level. When the idle signal IDLE transitions to a logic high level, the self-refresh signal generation unit 20 deactivates the internal self-refresh signal SREF to a logic low level in response to the toggling of the first internal clock signal ICLK2. As a result, the second clock buffer enable signal CLKBUF2_EN is activated to a logic high level, and the second clock buffer 28 starts toggling of the second internal clock signal CVR_CLK2.
Such a conventional clock control circuit requires two clock buffers in order to generate the necessary clock signals. Therefore, the two clock buffers must maintain the toggling operation state in almost all states, causing an undesirable current consumption.